A Boston startup called BoolSi closed a $6 million seed round on June 18 with a claim that cuts to the heart of one of computing’s most stubborn barriers: a software engineer can now mark a performance-critical function in their C or C++ application, and BoolSi’s compiler will return a custom hardware accelerator — a purpose-built chip coprocessor — generated in minutes without any knowledge of hardware description languages, digital logic, or circuit design. The round was led by Fine Structure Ventures, an F-Prime fund affiliated with Fidelity Investments, with Pillar VC, Fifth Quarter Ventures, and Coalition Ventures also participating.
The significance of that claim is easiest to understand through the problem it attacks. A general-purpose CPU pays a fixed overhead on every computation: it fetches an instruction, decodes it, and executes it — one instruction at a time, in sequence. That fetch-decode-execute cycle is the structural penalty of running flexible software on universal hardware. Custom digital logic sidesteps it entirely: dedicated gates and wires execute fixed computations in parallel, all at once, with no overhead. The performance difference can be dramatic. Until now, so has the design cost — putting custom hardware effectively out of reach for software developers.
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Custom FPGA compiler BoolSi closed a $6M seed round led by Fine Structure Ventures to give embedded software developers a path to custom silicon without hardware expertise. Rather than translating code structure, the compiler learns what a C function does and synthesizes FPGA hardware in minutes. Sign-ups open now for the Q3 2026 beta.
Field-programmable gate arrays — FPGAs, reconfigurable chips that can be reprogrammed after manufacturing — have offered a middle path since 1985: the flexibility of software with the parallelism of hardware, deployed without a costly semiconductor fabrication run. But programming an FPGA has always required writing in a hardware description language, typically VHDL or Verilog. That means learning to think about circuits rather than algorithms, specifying subcircuit coordination down to clock cycles, and working within a toolchain that assumes hardware expertise.
High-level synthesis tools — including AMD Vivado HLS, Siemens Catapult, and the open-source Bambu — tried to close that gap by accepting C or C++ code and generating VHDL or Verilog from it. They translate how the code is written, preserving the structure of the source program and mapping it onto register-transfer-level logic. That structural translation produces correct hardware, but it requires the developer to write C that cooperates with the synthesizer — adding pragma directives, restructuring loops, and organizing memory access patterns to help the tool. Software not specifically designed for HLS routinely underperforms hand-designed circuits. The barrier dropped in height but never disappeared.
BoolSi’s approach, developed by co-founder and CEO Mihailo Isakov and described publicly at ICCAD 2024 under the title “The Promise and Challenges of Designing Digital Logic through Backpropagation,” reframes the synthesis problem entirely. Rather than parsing code structure, BoolSi treats the source program as a black box and asks a different question: what input-output function does this code implement? The platform then synthesizes dedicated digital logic that implements exactly that function.
The mechanism that makes this possible is backpropagation — the same training algorithm that underlies deep learning. BoolSi uses the source program as a synthetic data generator: a fuzzer exhaustively explores the function’s input space, running the program on each input and recording the output. Every execution produces a precisely labeled training example. Those examples train a set of machine-learning models through backpropagation until the models converge into representations that can be expressed as fully digital circuits. Multiple independent models are trained in parallel and then formally verified against one another — a consensus check that substitutes for traditional RTL simulation and enforces complete functional accuracy across the generated hardware.
That last requirement matters structurally. Traditional HLS tools can produce hardware that approximates a source program’s behavior when the input doesn’t match what the pragma annotations expected. BoolSi’s approach cannot tolerate approximation: a hardware circuit that computes an incorrect answer is a broken circuit, not a slower one. The multi-model formal verification step exists precisely because learning from input-output traces is harder to guarantee than structural translation — and correctness is not negotiable.
BoolSi illustrates the performance ceiling with one benchmark: a 10,000-line C regex library scanning text for email addresses. Compiled with gcc -O3 on an ARM Cortex-A9 processor, the routine required 2.66 milliseconds. A single BoolSi hardware agent completed the same task in 0.325 milliseconds — roughly eight times faster. Eight agents running in parallel finished in 0.042 milliseconds, more than 63 times quicker than the CPU baseline, according to SiliconAngle.
The benchmark is one data point, and the regex workload suits fixed parallel hardware well — it has a bounded input alphabet and a deterministic function, which is precisely the profile that benefits most from BoolSi’s approach. Whether the technique generalizes cleanly to workloads with large or unbounded input spaces, complex control flow, or memory-dependent branching is a question the private beta will begin to answer.
BoolSi is targeting embedded developers in robotics first — teams whose applications hammer general-purpose processors with motor-control loops, sensor fusion, and model-predictive control at tight latency budgets. A private beta is scheduled to open in Q3 2026, with developer sign-ups available at boolsi.com. The company is starting with FPGAs because they ship immediately without a semiconductor fabrication run; the plan is to extend the toolchain to custom ASICs as production workload patterns become clear enough to justify fixed silicon.
The established tools — Vivado HLS, Catapult, Bambu — have made hardware engineers more productive but have not broadly admitted software developers to the hardware design process. Academic research on HLS performance gaps has consistently found that while HLS can achieve speedups of 4× to over 100× compared to software on benchmark kernels, designs produced from software not specifically written for HLS fall short of manually designed register-transfer-level circuits in performance, memory bandwidth, and logic utilization. BoolSi’s bet is that an approach that never sees the code structure — only the function’s input-output behavior — is less constrained by code style and requires less developer effort to exploit.
Fine Structure Ventures, which became an F-Prime Capital fund in July 2024 and counts semiconductor firms including Finwave Semiconductor in its portfolio, led the round. F-Prime Capital manages approximately $5.3 billion and focuses on frontier technology and healthcare. Pillar VC, Fifth Quarter Ventures, and Coalition Ventures also participated. BoolSi previously received backing from Intel Ignite, Intel’s deep tech startup accelerator. The company says proceeds will fund team expansion and development of the core toolchain.
What is BoolSi and how does its chip compiler work?
BoolSi is a Boston-based startup that builds a compiler for generating custom FPGA hardware accelerators from C or C++ functions. Instead of translating code structure into hardware description language, it uses backpropagation to train machine-learning models on the input-output behavior of the source program — treating the software as a black box — and then synthesizes those models into fully digital circuits. Multiple models are trained independently and formally cross-verified to enforce complete functional accuracy.
How is BoolSi different from existing high-level synthesis tools like Vivado HLS or Catapult?
Existing high-level synthesis tools translate how a program is written into hardware description language, requiring developers to add pragma annotations, restructure loops, and organize memory access for the synthesis tool. BoolSi skips the code structure entirely and learns what the function does from its input-output behavior. That distinction matters practically: a developer does not need to rewrite or annotate their code to use BoolSi’s compiler.
What developers and applications is BoolSi targeting?
BoolSi is initially aimed at embedded software developers in robotics, where workloads such as motor-control loops, sensor fusion, and model-predictive control create recurring CPU bottlenecks. The company is accepting sign-ups for a private beta scheduled to open in Q3 2026. The platform currently targets FPGAs, with a planned extension to custom ASICs as workload patterns become established.
What are the limitations of BoolSi’s approach?
BoolSi’s accuracy depends on the fuzzer achieving sufficiently exhaustive coverage of the function’s input space to produce correctly labeled training examples. Functions with very large or unbounded input spaces — or those with complex memory-dependent branching — present harder coverage challenges than the regex benchmark used in the company’s published performance data. The area efficiency of ML-synthesized circuits compared to hand-designed RTL is also an open engineering question that production deployments will test.
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